Hi Paweł,
On 11/7/20 13:14, Paweł Chmiel wrote:
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), fix this by calling
> clk_prepare_enable() directly from clock provider driver.
>
> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
> UFS module is probed before pmic used to power that device.
> In this case defer probe was happening and that clock was disabled by
> UFS driver, causing whole boot to hang on next CMU access.
>
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@xxxxxxxxx>
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -571,6 +572,10 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
> static void __init exynos7_clk_top1_init(struct device_node *np)
> {
> samsung_cmu_register_one(np, &top1_cmu_info);
> + /*
> + * Keep top FSYS1 aclk enabled permanently. It's required for CMU register access.
> + */
> + clk_prepare_enable(__clk_lookup("aclk_fsys1_200"));
Thanks for the patch. Could you rework it to avoid the __clk_lookup() call?
I.e. could you change it to something along the lines of:
-------------8<----------------
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 87ee1ba..9ecf498 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -570,7 +570,15 @@ static const struct samsung_cmu_info top1_cmu_info __initconst = {
static void __init exynos7_clk_top1_init(struct device_node *np)
{
- samsung_cmu_register_one(np, &top1_cmu_info);
+ struct samsung_clk_provider *ctx;
+ struct clk_hw **hws;
+
+ ctx = samsung_cmu_register_one(np, &top1_cmu_info);
+ if (!ctx)
+ return;
+ hws = ctx->clk_data.hws;
+
+ clk_prepare_enable(hws[CLK_ACLK_FSYS1_200]);
}
CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
-------------8<----------------
?
--
Regards,
Sylwester
