Hi Rob, On 04.11.2020 22:35, Rob Herring wrote: > On Thu, Oct 29, 2020 at 02:40:13PM +0100, Marek Szyprowski wrote: >> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433 >> variant). Based on the text dt-binding posted by Jaehoon Chung. >> >> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx> >> Reviewed-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> >> --- >> .../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++++++++++++++ >> 1 file changed, 119 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml >> ... >> + num-viewport: >> + const: 3 > I'm confused why you need this. This is only used with the iATU except > for keystone. Platforms like Exynos with their own child bus config > space accessors don't have an iATU. Frankly I have no idea, I don't know much about the PCI internals. After rebasing onto your latest DW PCI changes I've noticed a following warning message: exynos-pcie 15700000.pcie: Resources exceed number of ATU entries (2) Here is a complete log: # dmesg | grep pci ehci-pci: EHCI PCI platform driver ohci-pci: OHCI PCI platform driver exynos-pcie 15700000.pcie: host bridge /soc@0/pcie@15700000 ranges: exynos-pcie 15700000.pcie: IO 0x000c001000..0x000c010fff -> 0x0000000000 exynos-pcie 15700000.pcie: MEM 0x000c011000..0x000ffffffe -> 0x000c011000 exynos-pcie 15700000.pcie: Resources exceed number of ATU entries (2) exynos-pcie 15700000.pcie: Link up exynos-pcie 15700000.pcie: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [bus 00-ff] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] pci_bus 0000:00: root bus resource [mem 0x0c011000-0x0ffffffe] pci 0000:00:00.0: [144d:a5e3] type 01 class 0x060400 pci 0000:00:00.0: PME# supported from D0 D3hot D3cold pci 0000:01:00.0: [14e4:43e9] type 00 class 0x028000 pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x003fffff 64bit] pci 0000:01:00.0: supports D1 D2 pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:00.0: BAR 14: assigned [mem 0x0c200000-0x0c7fffff] pci 0000:01:00.0: BAR 2: assigned [mem 0x0c400000-0x0c7fffff 64bit] pci 0000:01:00.0: BAR 0: assigned [mem 0x0c200000-0x0c207fff 64bit] pci 0000:00:00.0: PCI bridge to [bus 01-ff] pci 0000:00:00.0: bridge window [mem 0x0c200000-0x0c7fffff] pci 0000:00:00.0: MSI quirk detected; MSI disabled pcieport 0000:00:00.0: PME: Signaling with IRQ 97 brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac4358-pcie for chip BCM4358/1 When I've increased the numer of viewports it has gone. If this is not the proper solution, I will removed it. Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland
