Exynos4-IS driver relies on the way the ARM DMA-IOMMU glue code works:
the IOVA allocator uses first-fit algorithm and the first allocated
buffer is at 0x0 DMA/IOVA address. This is not true for the generic
IOMMU-DMA glue code that will be used for ARM architecture soon, so add
the needed code to support such case too.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
---
drivers/media/platform/exynos4-is/fimc-is.c | 95 ++++++++++++++++++---
drivers/media/platform/exynos4-is/fimc-is.h | 6 +-
2 files changed, 88 insertions(+), 13 deletions(-)
diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c
index 41b841a96338..bdef61be0cad 100644
--- a/drivers/media/platform/exynos4-is/fimc-is.c
+++ b/drivers/media/platform/exynos4-is/fimc-is.c
@@ -19,6 +19,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
+#include <linux/iommu.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_graph.h>
@@ -269,7 +270,7 @@ int fimc_is_cpu_set_power(struct fimc_is *is, int on)
mcuctl_write(0, is, REG_WDT_ISP);
/* Cortex-A5 start address setting */
- mcuctl_write(is->memory.addr, is, MCUCTL_REG_BBOAR);
+ mcuctl_write(is->memory.base, is, MCUCTL_REG_BBOAR);
/* Enable and start Cortex-A5 */
pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
@@ -330,37 +331,105 @@ int fimc_is_start_firmware(struct fimc_is *is)
return ret;
}
+#ifdef CONFIG_IOMMU_DMA
+#define FIMC_IS_CPU_MEM_BASE (0)
+static int fimc_iommu_remap_cpu_memory(struct fimc_is *is)
+{
+ struct device *dev = &is->pdev->dev;
+ struct iommu_domain *domain;
+ struct sg_table sgt;
+ int ret;
+
+ domain = iommu_domain_alloc(&platform_bus_type);
+ if (!domain)
+ return -ENOMEM;
+
+ ret = dma_get_sgtable(dev, &sgt, is->memory.vaddr,
+ is->memory.alloc_addr, FIMC_IS_CPU_MEM_SIZE);
+ if (ret)
+ goto err_free_domain;
+
+ ret = iommu_attach_device(domain, dev);
+ if (ret)
+ goto err_free_sgt;
+
+ ret = iommu_map_sgtable(domain, FIMC_IS_CPU_MEM_BASE, &sgt,
+ IOMMU_READ | IOMMU_WRITE);
+ if (ret != FIMC_IS_CPU_MEM_SIZE) {
+ ret = -EINVAL;
+ goto err_detach;
+ }
+
+ is->memory.base = FIMC_IS_CPU_MEM_BASE;
+ is->memory.domain = domain;
+ sg_free_table(&sgt);
+
+ return 0;
+
+err_detach:
+ iommu_detach_device(domain, dev);
+err_free_sgt:
+ sg_free_table(&sgt);
+err_free_domain:
+ iommu_domain_free(domain);
+ return ret;
+}
+
+static void fimc_iommu_unmap_cpu_memory(struct fimc_is *is)
+{
+ struct iommu_domain *domain = is->memory.domain;
+ struct device *dev = &is->pdev->dev;
+
+ iommu_unmap(domain, FIMC_IS_CPU_MEM_BASE, FIMC_IS_CPU_MEM_SIZE);
+ iommu_detach_device(domain, dev);
+ iommu_domain_free(domain);
+}
+#else
+static inline int fimc_iommu_remap_cpu_memory(struct fimc_is *is)
+{
+ is->memory.base = is->memory.alloc_addr;
+ return 0;
+}
+
+static void fimc_iommu_unmap_cpu_memory(struct fimc_is *is) { }
+#endif
+
/* Allocate working memory for the FIMC-IS CPU. */
static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
{
struct device *dev = &is->pdev->dev;
is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
- &is->memory.addr, GFP_KERNEL);
+ &is->memory.alloc_addr, GFP_KERNEL);
if (is->memory.vaddr == NULL)
return -ENOMEM;
+ if (fimc_iommu_remap_cpu_memory(is))
+ goto err;
+
is->memory.size = FIMC_IS_CPU_MEM_SIZE;
- dev_info(dev, "FIMC-IS CPU memory base: %pad\n", &is->memory.addr);
+ dev_info(dev, "FIMC-IS CPU memory base: %pad\n", &is->memory.base);
- if (((u32)is->memory.addr) & FIMC_IS_FW_ADDR_MASK) {
+ if (((u32)is->memory.base) & FIMC_IS_FW_ADDR_MASK) {
dev_err(dev, "invalid firmware memory alignment: %#x\n",
- (u32)is->memory.addr);
- dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
- is->memory.addr);
- return -EIO;
+ (u32)is->memory.base);
+ goto err;
}
is->is_p_region = (struct is_region *)(is->memory.vaddr +
FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
- is->is_dma_p_region = is->memory.addr +
+ is->is_dma_p_region = is->memory.base +
FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
FIMC_IS_SHARED_REGION_OFFSET);
return 0;
+err:
+ dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
+ is->memory.alloc_addr);
+ return -EIO;
}
static void fimc_is_free_cpu_memory(struct fimc_is *is)
@@ -370,8 +439,9 @@ static void fimc_is_free_cpu_memory(struct fimc_is *is)
if (is->memory.vaddr == NULL)
return;
+ fimc_iommu_unmap_cpu_memory(is);
dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
- is->memory.addr);
+ is->memory.alloc_addr);
}
static void fimc_is_load_firmware(const struct firmware *fw, void *context)
@@ -416,7 +486,8 @@ static void fimc_is_load_firmware(const struct firmware *fw, void *context)
dev_info(dev, "loaded firmware: %s, rev. %s\n",
is->fw.info, is->fw.version);
- dev_dbg(dev, "FW size: %zu, DMA addr: %pad\n", fw->size, &is->memory.addr);
+ dev_dbg(dev, "FW size: %zu, DMA addr: %pad\n", fw->size,
+ &is->memory.base);
is->is_shared_region->chip_id = 0xe4412;
is->is_shared_region->chip_rev_no = 1;
@@ -699,7 +770,7 @@ int fimc_is_hw_initialize(struct fimc_is *is)
}
pr_debug("shared region: %pad, parameter region: %pad\n",
- &is->memory.addr + FIMC_IS_SHARED_REGION_OFFSET,
+ &is->memory.base + FIMC_IS_SHARED_REGION_OFFSET,
&is->is_dma_p_region);
is->setfile.sub_index = 0;
diff --git a/drivers/media/platform/exynos4-is/fimc-is.h b/drivers/media/platform/exynos4-is/fimc-is.h
index ce30b007bc55..e96bf9122e91 100644
--- a/drivers/media/platform/exynos4-is/fimc-is.h
+++ b/drivers/media/platform/exynos4-is/fimc-is.h
@@ -186,11 +186,15 @@ struct fimc_is_firmware {
struct fimc_is_memory {
/* DMA base address */
- dma_addr_t addr;
+ dma_addr_t base;
+ /* DMA address from allocator */
+ dma_addr_t alloc_addr;
/* virtual base address */
void *vaddr;
/* total length */
unsigned int size;
+ /* optional IOMMU domain */
+ struct iommu_domain *domain;
};
#define FIMC_IS_I2H_MAX_ARGS 12
--
2.17.1
