Hi Marc,
On 14.09.2020 15:13, Marc Zyngier wrote:
> On 2020-09-14 14:06, Marek Szyprowski wrote:
>> On 01.09.2020 16:43, Marc Zyngier wrote:
>>> Change the way we deal with GIC SGIs by turning them into proper
>>> IRQs, and calling into the arch code to register the interrupt range
>>> instead of a callback.
>>>
>>> Reviewed-by: Valentin Schneider <valentin.schneider@xxxxxxx>
>>> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
>> This patch landed in linux next-20200914 as commit ac063232d4b0
>> ("irqchip/gic: Configure SGIs as standard interrupts"). Sadly it breaks
>> booting of all Samsung Exynos 4210/4412 based boards (dual/quad ARM
>> Cortex A9 based). Here are the last lines from the bootlog:
>>
>> [ 0.106322] CPU: Testing write buffer coherency: ok
>> [ 0.109895] CPU0: Spectre v2: using BPIALL workaround
>> [ 0.116057] CPU0: thread -1, cpu 0, socket 9, mpidr 80000900
>> [ 0.123885] Setting up static identity map for 0x40100000 -
>> 0x40100060
>> [ 0.130191] rcu: Hierarchical SRCU implementation.
>> [ 0.137195] soc soc0: Exynos: CPU[EXYNOS4210] PRO_ID[0x43210211]
>> REV[0x11] Detected
>> [ 0.145129] smp: Bringing up secondary CPUs ...
>> [ 0.156279] CPU1: thread -1, cpu 1, socket 9, mpidr 80000901
>> [ 0.156291] CPU1: Spectre v2: using BPIALL workaround
>> [ 2.716379] random: fast init done
>
> Thanks for the report. Is this the funky non-banked GIC?
Both Exynos 4210 and 4412 use non-zero cpu-offset in GIC node in
device-tree: arch/arm/boot/dts/exynos{4210,4412}.dtsi, so I assume that
the GIC registers are not banked.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
