On 8/19/20 05:14, Stephen Boyd wrote:
Quoting Marek Szyprowski (2020-08-07 06:31:43)
BPLL clock must not be disabled because it is needed for proper DRAM
operation. This is normally handled by respective memory devfreq driver,
but when that driver is not yet probed or its probe has been deferred the
clock might got disabled what causes board hang. Fix this by calling
clk_prepare_enable() directly from the clock provider driver.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
Reviewed-by: Lukasz Luba <lukasz.luba@xxxxxxx>
Tested-by: Lukasz Luba <lukasz.luba@xxxxxxx>
Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
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Can I pick this up for clk-fixes?
Sure, thanks for taking care of this.
