On Wed, Aug 05, 2020 at 11:16:01AM +0200, Marek Szyprowski wrote: > BPLL clock must not be disabled because it is needed for proper DRAM > operation. This is normally handled by respective memory devfreq driver, > but when that driver is not yet probed or its probe has been deferred the > clock might got disabled what causes board hang. Fix this by marking it > as critical. > > Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx> > --- > drivers/clk/samsung/clk-exynos5420.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> Best regards, Krzysztof
