On 4/25/2020 11:06 PM, Jonathan Bakker wrote:
> The USB phy takes some time to reset, so make sure we give it to it. The
> delay length was taken from the 4x12 phy driver.
>
> This manifested in issues with the DWC2 driver since commit fe369e1826b3
> ("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.")
> where the endianness check would read the DWC ID as 0 due to the phy still
> resetting, resulting in the wrong endian mode being chosen.
>
> Signed-off-by: Jonathan Bakker <xc-racer2@xxxxxxx>
merged, thanks!
-Kishon
> ---
> drivers/phy/samsung/phy-s5pv210-usb2.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/phy/samsung/phy-s5pv210-usb2.c b/drivers/phy/samsung/phy-s5pv210-usb2.c
> index 56a5083fe6f9..32be62e49804 100644
> --- a/drivers/phy/samsung/phy-s5pv210-usb2.c
> +++ b/drivers/phy/samsung/phy-s5pv210-usb2.c
> @@ -139,6 +139,10 @@ static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
> udelay(10);
> rst &= ~rstbits;
> writel(rst, drv->reg_phy + S5PV210_UPHYRST);
> + /* The following delay is necessary for the reset sequence to be
> + * completed
> + */
> + udelay(80);
> } else {
> pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
> pwr |= phypwr;
>
