Hi!
On 5/6/20 10:02 AM, Hyunki Koo wrote:
> Support 32-bit access for the TX/RX hold registers UTXH and URXH.
>
> This is required for some newer SoCs.
Krzysztof has asked this previously but I couldn't find the answer in
previous mails:
Do you plan to upstream support for these newer SoCs?
If not (i.e. this code is only to support Android GKI) then the code
you are adding now may be removed at any time later during cleanups
(due to lack of the in-kernel users).
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> Signed-off-by: Hyunki Koo <hyunki00.koo@xxxxxxxxxxx>
> Reviewed-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> Tested on Odroid HC1 (Exynos5422):
> Tested-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
> ---
> drivers/tty/serial/samsung_tty.c | 62 ++++++++++++++++++++++++++++++++++++----
> 1 file changed, 57 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index 326b0164609c..6ef614d8648c 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -154,10 +154,33 @@ struct s3c24xx_uart_port {
> #define portaddrl(port, reg) \
> ((unsigned long *)(unsigned long)((port)->membase + (reg)))
>
> -#define rd_reg(port, reg) (readb_relaxed(portaddr(port, reg)))
> +static u32 rd_reg(struct uart_port *port, u32 reg)
> +{
> + switch (port->iotype) {
> + case UPIO_MEM:
> + return readb_relaxed(portaddr(port, reg));
> + case UPIO_MEM32:
> + return readl_relaxed(portaddr(port, reg));
> + default:
> + return 0;
> + }
> + return 0;
> +}
> +
> #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
>
> -#define wr_reg(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
> +static void wr_reg(struct uart_port *port, u32 reg, u32 val)
> +{
> + switch (port->iotype) {
> + case UPIO_MEM:
> + writeb_relaxed(val, portaddr(port, reg));
> + break;
> + case UPIO_MEM32:
> + writel_relaxed(val, portaddr(port, reg));
> + break;
> + }
> +}
> +
> #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
>
> /* Byte-order aware bit setting/clearing functions. */
> @@ -1974,7 +1997,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev)
> struct device_node *np = pdev->dev.of_node;
> struct s3c24xx_uart_port *ourport;
> int index = probe_index;
> - int ret;
> + int ret, prop = 0;
>
> if (np) {
> ret = of_alias_get_id(np, "serial");
> @@ -2000,10 +2023,27 @@ static int s3c24xx_serial_probe(struct platform_device *pdev)
> dev_get_platdata(&pdev->dev) :
> ourport->drv_data->def_cfg;
>
> - if (np)
> + if (np) {
> of_property_read_u32(np,
> "samsung,uart-fifosize", &ourport->port.fifosize);
>
> + if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
> + switch (prop) {
> + case 1:
> + ourport->port.iotype = UPIO_MEM;
> + break;
> + case 4:
> + ourport->port.iotype = UPIO_MEM32;
> + break;
> + default:
> + dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
> + prop);
> + ret = -EINVAL;
> + break;
> + }
> + }
> + }
> +
> if (ourport->drv_data->fifosize[index])
> ourport->port.fifosize = ourport->drv_data->fifosize[index];
> else if (ourport->info->fifosize)
> @@ -2587,6 +2627,18 @@ module_platform_driver(samsung_serial_driver);
> * Early console.
> */
>
> +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
> +{
> + switch (port->iotype) {
> + case UPIO_MEM:
> + writeb(val, portaddr(port, reg));
> + break;
> + case UPIO_MEM32:
> + writel(val, portaddr(port, reg));
> + break;
> + }
> +}
> +
> struct samsung_early_console_data {
> u32 txfull_mask;
> };
> @@ -2612,7 +2664,7 @@ static void samsung_early_putc(struct uart_port *port, int c)
> else
> samsung_early_busyuart(port);
>
> - writeb(c, port->membase + S3C2410_UTXH);
> + wr_reg_barrier(port, S3C2410_UTXH, c);
> }
>
> static void samsung_early_write(struct console *con, const char *s,
>
