> + struct exynos_ufs_drv_data *drv_data; > + > + u32 opts; > +#define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0) > +#define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB BIT(1) > +#define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2) > +#define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3) > +#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) Could not find where the last 2 are being used. Thanks, Avri