Hi Rob, > -----Original Message----- > From: Rob Herring <robh@xxxxxxxxxx> > Sent: 05 April 2020 07:24 > To: Alim Akhtar <alim.akhtar@xxxxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx; linux-scsi@xxxxxxxxxxxxxxx; krzk@xxxxxxxxxx; > avri.altman@xxxxxxx; martin.petersen@xxxxxxxxxx; > kwmad.kim@xxxxxxxxxxx; stanley.chu@xxxxxxxxxxxx; > cang@xxxxxxxxxxxxxx; linux-samsung-soc@xxxxxxxxxxxxxxx; linux-arm- > kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx > Subject: Re: [PATCH v4 1/5] dt-bindings: phy: Document Samsung UFS PHY > bindings > > On Fri, Mar 27, 2020 at 10:36:34PM +0530, Alim Akhtar wrote: > > This patch documents Samsung UFS PHY device tree bindings > > > > Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx> > > --- > > .../bindings/phy/samsung,ufs-phy.yaml | 67 +++++++++++++++++++ > > 1 file changed, 67 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > > b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > > new file mode 100644 > > index 000000000000..41ba481ecc76 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > > @@ -0,0 +1,67 @@ > > +# SPDX-License-Identifier: (GPL-2.0) > > Dual license new bindings: > > (GPL-2.0-only OR BSD-2-Clause) > Sure will update. > > +%YAML 1.2 > > +--- > > +$id: > > +https://protect2.fireeye.com/url?k=91cb53a2-cc1b5b6e-91cad8ed-000babf > > +f3793- > 448c7d85bdf69f5a&q=1&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2F > > +phy%2Fsamsung%2Cufs-phy.yaml%23 > > +$schema: > > +https://protect2.fireeye.com/url?k=a8ce57c7-f51e5f0b-a8cfdc88-000babf > > +f3793-fbe649ab0853d701&q=1&u=http%3A%2F%2Fdevicetree.org%2Fmeta- > schem > > +as%2Fcore.yaml%23 > > + > > +title: Samsung SoC series UFS PHY Device Tree Bindings > > + > > +maintainers: > > + - Alim Akhtar <alim.akhtar@xxxxxxxxxxx> > > + > > +properties: > > + "#phy-cells": > > + const: 0 > > + > > + compatible: > > + enum: > > + - samsung,exynos7-ufs-phy > > + > > + reg: > > + maxItems: 1 > > + description: PHY base register address > > + > > + reg-names: > > + items: > > + - const: phy-pma > > + > > + clocks: > > + items: > > + - description: PLL reference clock > > + - description: Referencec clock parrent > > + > > + clock-names: > > + items: > > + - const: ref_clk_parent > > + - const: ref_clk > > Doesn't match what 'clocks' says. > Will correct. > Also, why do you need the parent in DT? Just use clk_get_parent(). DT should > reflect actual h/w clock connections (not what the driver happens to need). > Also, there's the assigned-clocks binding. > Some of the platform deviates from the normal clock trees and need to force a different parent. To get such parent added this. I will explore a bit more on this, and check about assigned-clocks binding. This is also an optional clock, so will change accordingly > > + > > + samsung,pmu-syscon: > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > + description: phandle for PMU system controller interface, used to > > + control pmu registers for power isolation > > We have a binding for power domains. Use that for power isolation. > Let me have a look on that, if power domains bindings can be use here, this is same way other Exynos binding is defined w.r.t. pmu-syscon. > > + > > +required: > > + - "#phy-cells" > > + - compatible > > + - reg > > + - reg-names > > + - clocks > > + - clock-names > > + - samsung,pmu-syscon > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/exynos7-clk.h> > > + > > + ufs_phy: ufs-phy@15571800 { > > + compatible = "samsung,exynos7-ufs-phy"; > > + reg = <0x15571800 0x240>; > > + reg-names = "phy-pma"; > > + samsung,pmu-syscon = <&pmu_system_controller>; > > + #phy-cells = <0>; > > + clocks = <&clock_fsys1 MOUT_FSYS1_PHYCLK_SEL1>, > > + <&clock_top1 CLK_SCLK_PHY_FSYS1_26M>; > > + clock-names = "ref_clk_parent", > > + "ref_clk"; > > + }; > > +... > > > > base-commit: fb33c6510d5595144d585aa194d377cf74d31911 > > -- > > 2.17.1 > >
