Allow setting the number of cycles for RAM reads in the pl310 cache controller L2 auxiliary control register mask (bits 0-2) since it needs to be changed in software. This only affects exynos4210 and exynos4412 as they use the pl310 cache controller. With the mask used until now, the following warnings were generated, the 2nd one being a pr_alert(): L2C: platform modifies aux control register: 0x02070000 -> 0x3e470001 L2C: platform provided aux values permit register corruption. This latency cycles value has always been set in software in spite of the warnings. Keep it this way but clear the alert message about register corruption to acknowledge it is a valid thing to do. Tested on exynos4412-odroid-x2. Signed-off-by: Guillaume Tucker <guillaume.tucker@xxxxxxxxxxxxx> Reported-by: "kernelci.org bot" <bot@xxxxxxxxxxxx> --- arch/arm/mach-exynos/exynos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 7a8d1555db40..ed1bba49210d 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -194,7 +194,7 @@ static void __init exynos_dt_fixup(void) DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)") .l2c_aux_val = 0x3c400001, - .l2c_aux_mask = 0xc20fffff, + .l2c_aux_mask = 0xc20ffff8, .smp = smp_ops(exynos_smp_ops), .map_io = exynos_init_io, .init_early = exynos_firmware_init, -- 2.20.1
