Hi Krzysztof, On Sat, 14 Mar 2020 at 23:50, Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote: > > On Sat, Mar 14, 2020 at 07:02:33PM +0530, Anand Moon wrote: > > Hi Krzysztof, > > > > On Wed, 11 Mar 2020 at 01:19, Anand Moon <linux.amoon@xxxxxxxxx> wrote: > > > > > > Add new compatible strings for USBDRD3 for adding missing > > > suspend clk, exynos5422 usbdrd3 support two clk USBD300 and > > > SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes. > > > > > > Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx> > > > > My assumption based on the FSYS clock source diagram below was bit wrong. > > [0] https://imgur.com/gallery/zAiBoyh > > > > And again re-looking into the driver source code, it turn out their > > are *6 clock* > > Here is the correct mapping as per the Exynos5420 clock driver. > > > > USB-(phy@12100000) > > |___________________CLK_SCLK_USBD300 > > |___________________CLK_SCLK_USBPHY300 > > > > USB-(phy@12500000) > > |___________________CLK_SCLK_USBD301 > > |___________________CLK_SCLK_USBPHY301 > > > > USB-(dwc3@12000000) > > |___________________CLK_USBD300 > > USB-(dwc3@12400000) > > |___________________CLK_USBD301 > > > > Note: As per Exynos 5422 user manual, There are some more USB CLK > > configuration missing in GATE_IP_FSYS. So we could enable another dwc3 clk, > > If needed I would like too add this missing clk code and enable this > > clk for dwc3 driver. > > > > For some reason we already use CLK_USBD300 and CLK_USBD301 > > for PHY nodes, which lead to this confusion. So we need to update PHY clock > > CLK_USBD300 with CLK_SCLK_USBD300 and clock CLK_USBD301 with CLK_SCLK_USBD301. > > > > Please share your thought on linking PHY nodes above and add new DWC3 clock > > and enable this clock. > > The real clock topology of Exynos5422 is not properly reflected in the > kernel. However cleaning this up is quite big task. > > > Best regards, > Krzysztof > I would like to fix all my patches with new finding and submit them once again for review. -Anand
