Move FSYS2 clk setting to sub-CMU block to support power domain on/off
sequences for mmc driver.
Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
---
Note: This patch might be missing some more setting
as suspend/resume feature is broken.
I could not resolve this issue at my end, any input or
suggetion to improve this code.
---
drivers/clk/samsung/clk-exynos5420.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c9e5a1fb6653..3597e8d62445 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1035,9 +1035,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
- GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
- GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
- GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
@@ -1258,6 +1255,17 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
{ DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
};
+static const struct samsung_gate_clock exynos5x_fsys2_gate_clks[] __initconst = {
+ GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
+ GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
+ GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_fsys2_suspend_regs[] = {
+ { GATE_IP_FSYS, 0xff, 0xff }, /* FSYS gates */
+ { SRC_TOP3, 0, BIT(12) }, /* MUX_ACLK_200_FSYS2_SEL */
+};
+
static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
CLK_SET_RATE_PARENT, 0),
@@ -1376,12 +1384,21 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
.pd_name = "MAU",
};
+static const struct exynos5_subcmu_info exynos5x_fsys2_subcmu = {
+ .gate_clks = exynos5x_fsys2_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(exynos5x_fsys2_gate_clks),
+ .suspend_regs = exynos5x_fsys2_suspend_regs,
+ .nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys2_suspend_regs),
+ .pd_name = "FSYS2",
+};
+
static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
&exynos5x_disp_subcmu,
&exynos5x_gsc_subcmu,
&exynos5x_g3d_subcmu,
&exynos5x_mfc_subcmu,
&exynos5x_mscl_subcmu,
+ &exynos5x_fsys2_subcmu,
};
static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
@@ -1391,6 +1408,7 @@ static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
&exynos5x_mfc_subcmu,
&exynos5x_mscl_subcmu,
&exynos5800_mau_subcmu,
+ &exynos5x_fsys2_subcmu,
};
static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
--
2.25.0
