Quoting Marek Szyprowski (2019-12-16 05:14:07) > In Exynos542x/5800 SoCs, the G3D leaf clocks are located in the G3D power > domain. This is similar to the other hardware modules and their power > domains. However there is one thing specific to G3D clocks hierarchy. > Unlike other hardware modules, the G3D clocks hierarchy doesn't have any > gate clock between the TOP part of the hierarchy and the part located in > the power domain and some SoC internal busses are sourced directly from > the TOP muxes. The consequence of this design if the fact that the TOP > part of the hierarchy has to be enabled permanently to ensure proper > operation of the SoC power related components (G3D power domain and > Exynos Power Management Unit for system suspend/resume). > > This patch adds an explicit call to clk_prepare_enable() on the last MUX > in the TOP part of G3D clock hierarchy to keep it enabled permanently to > ensure that the internal busses get their clock regardless of the main > G3D clock enablement status. > > This fixes following imprecise abort issue observed on Odroid XU3/XU4 > after enabling Panfrost driver by commit 1a5a85c56402 "ARM: dts: exynos: > Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"): > > panfrost 11800000.gpu: clock rate = 400000000 > panfrost 11800000.gpu: failed to get regulator: -517 > panfrost 11800000.gpu: regulator init failed -517 > Power domain G3D disable failed > ... > panfrost 11800000.gpu: clock rate = 400000000 > 8<--- cut here --- Applied to clk-fixes
