On 10/25/19 11:34, Marek Szyprowski wrote: > Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D, > so the G3D MALI driver can simply adjust the rate of its clock by doing > a single clk_set_rate() call, without the need to know the whole clock > topology in Exynos542x SoCs. > > Suggested-by: Marian Mihailescu <mihailescu2m@xxxxxxxxx> > Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx> Patch applied, thank you.
