On 10/29/19 01:50, Marian Mihailescu wrote:
> Save and restore top PLL related configuration registers for big (APLL)
> and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks
> were reset to default values after suspend/resume cycle and performance
> after system resume was affected when performance governor has been selected.
>
> Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list")
> Signed-off-by: Marian Mihailescu <mihailescu2m@xxxxxxxxx>
Patch applied, thank you.
Please remember to also Cc in future any clk patches to the linux-clk@xxxxxxxxxxxxxxx
mailing list.
> ---
> drivers/clk/samsung/clk-exynos5420.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 403b5a367a5b..3a991ca1ee36 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -165,6 +165,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
> GATE_BUS_CPU,
> GATE_SCLK_CPU,
> CLKOUT_CMU_CPU,
> + APLL_CON0,
> + KPLL_CON0,
> CPLL_CON0,
> DPLL_CON0,
> EPLL_CON0,
