On Wed, Oct 23, 2019 at 09:41:18AM +0200, Marek Szyprowski wrote:
> G3D clocks require special handling of their parent bus clock during power
> domain on/off sequences. Those clocks were not initially added to the
> sub-CMU handler, because that time there was no open-source driver for the
> G3D (MALI Panfrost) hardware module and it was not possible to test it.
>
> This patch fixes this issue. Parent clock for G3D hardware block is now
> properly preserved during G3D power domain on/off sequence. This restores
> proper MALI Panfrost performance broken by commit 8686764fc071
> ("ARM: dts: exynos: Add G3D power domain to Exynos542x").
>
> Reported-by: Marian Mihailescu <mihailescu2m@xxxxxxxxx>
> Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver")
> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> Tested-by: Marian Mihailescu <mihailescu2m@xxxxxxxxx>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
Best regards,
Krzysztof
