On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx> wrote: > > Change the parents of UART clocks to the CPLL which has 666MHz. > The UARTs' dividers use /10 rate so they would have 66.6MHz. Write also the state before to show what is being fixed (I assume previous frequency was not best choice). BR, Krzysztof
