On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx> wrote: > > Add an OPP for FSYS APB which reflects the real possible frequency. > The bus will have a new parent clock which speed has 600MHz, thus > a new possible frequency provided by the clock divider is 150MHz. > According to the documentation max possible frequency for this bus is > 200MHz. Commit msg is good but title could be improved. Focus in the title what problem/issue you are solving - add intermediate step in scaling of FSYS APB? Best regards, Krzysztof
