Update the bus_disp1 OPPs and add 400MHz which is max frequency for this
bus. The frequencies are aligned to parent clock such that it is not
needed to change the PLL rate.
Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/exynos5420.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 2b36c2f77a10..6e82ffcbeacd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1305,7 +1305,7 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <120000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
@@ -1313,6 +1313,9 @@
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
+ opp03 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
};
bus_gscl_opp_table: opp_table15 {
--
2.17.1
