During early system resume on Exynos5422 with performance counters enabled
the following kernel oops happens:
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 1433 Comm: bash Tainted: G W 5.0.0-rc5-next-20190208-00023-gd5fb5a8a13e6-dirty #5480
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
PC is at reset_ctrl_regs+0x128/0x354
LR is at reset_ctrl_regs+0x124/0x354
pc : [<c0112814>] lr : [<c0112810>] psr: 600001d3
...
Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 4451006a DAC: 00000051
Process bash (pid: 1433, stack limit = 0xb7e0e22f)
...
[<c0112814>] (reset_ctrl_regs) from [<c0112ad0>] (dbg_cpu_pm_notify+0x1c/0x24)
[<c0112ad0>] (dbg_cpu_pm_notify) from [<c014c840>] (notifier_call_chain+0x44/0x84)
[<c014c840>] (notifier_call_chain) from [<c014cbc0>] (__atomic_notifier_call_chain+0x7c/0x128)
[<c014cbc0>] (__atomic_notifier_call_chain) from [<c01ffaac>] (cpu_pm_notify+0x30/0x54)
[<c01ffaac>] (cpu_pm_notify) from [<c055116c>] (syscore_resume+0x98/0x3f4)
[<c055116c>] (syscore_resume) from [<c0189350>] (suspend_devices_and_enter+0x97c/0xe74)
[<c0189350>] (suspend_devices_and_enter) from [<c0189fb8>] (pm_suspend+0x770/0xc04)
[<c0189fb8>] (pm_suspend) from [<c0187740>] (state_store+0x6c/0xcc)
[<c0187740>] (state_store) from [<c09fa698>] (kobj_attr_store+0x14/0x20)
[<c09fa698>] (kobj_attr_store) from [<c030159c>] (sysfs_kf_write+0x4c/0x50)
[<c030159c>] (sysfs_kf_write) from [<c0300620>] (kernfs_fop_write+0xfc/0x1e0)
[<c0300620>] (kernfs_fop_write) from [<c0282be8>] (__vfs_write+0x2c/0x160)
[<c0282be8>] (__vfs_write) from [<c0282ea4>] (vfs_write+0xa4/0x16c)
[<c0282ea4>] (vfs_write) from [<c0283080>] (ksys_write+0x40/0x8c)
[<c0283080>] (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x28)
...
---[ end trace 03fc9866185939bf ]---
Undefined instruction is triggered during CP14 reset, because bits: #16
(Secure privileged invasive debug disabled) and #17 (Secure privileged
noninvasive debug disable) are set in DSCR. Those bits depend on SPNIDEN
and SPIDEN lines, which are provided by Secure JTAG hardware block. That
block in turn is powered from cluster 0 (big/Eagle), but the Exynos5422
boots on cluster 1 (LITTLE/KFC).
To fix this issue it is enough to turn on the power on the cluster 0 for
a while. This lets the Secure JTAG block to propagate the needed signals
to LITTLE/KFC cores and change their DSCR.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
---
arch/arm/mach-exynos/suspend.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 3ac84f621d99..ef0c750f746c 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -449,8 +449,27 @@ static void exynos3250_pm_resume(void)
static void exynos5420_prepare_pm_resume(void)
{
+ unsigned int mpidr, cluster;
+
+ mpidr = read_cpuid_mpidr();
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
WARN_ON(mcpm_cpu_powered_up());
+
+ if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
+ /*
+ * When system is resumed on the LITTLE/KFC core (cluster 1),
+ * the DSCR is not properly updated until the power is turned
+ * on also for the cluster 0. Enable it for a while to
+ * propagate the SPNIDEN and SPIDEN signals from Secure JTAG
+ * block and avoid undefined instruction issue on CP14 reset.
+ */
+ pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ EXYNOS_COMMON_CONFIGURATION(0));
+ pmu_raw_writel(0,
+ EXYNOS_COMMON_CONFIGURATION(0));
+ }
}
static void exynos5420_pm_resume(void)
--
2.17.1
