Hi Marek,
On 19. 2. 15. 오후 9:52, Marek Szyprowski wrote:
> All CortexA7/A15 based Exynos SoCs have ARM architected timers, so enable
> support for them directly in the base dtsi for Exynos3250, Exynos5250
> and Exynos54xx SoCs. None of the known firmware properly configures arch
> timer registers, so mark them as not-fw-configured and set frequency
> to 24MHz, which is the only configuration supported by the remaining
> drivers (clocks) so far.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/exynos3250.dtsi | 10 ++++++++++
> arch/arm/boot/dts/exynos5250.dtsi | 1 +
> arch/arm/boot/dts/exynos54xx.dtsi | 10 ++++++++++
> 3 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index 608d17454179..3966e7960964 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -134,6 +134,16 @@
> };
> };
>
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <24000000>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> sysram@2020000 {
> compatible = "mmio-sram";
> reg = <0x02020000 0x40000>;
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 80986b97dfe5..95af4050f69d 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -239,6 +239,7 @@
> * so we need the value from DT.
> */
> clock-frequency = <24000000>;
> + arm,cpu-registers-not-fw-configured;
> };
>
> mct@101c0000 {
> diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
> index de26e5ee0d2d..45e06717ee51 100644
> --- a/arch/arm/boot/dts/exynos54xx.dtsi
> +++ b/arch/arm/boot/dts/exynos54xx.dtsi
> @@ -46,6 +46,16 @@
> status = "disabled";
> };
>
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + arm,cpu-registers-not-fw-configured;
> + clock-frequency = <24000000>;
> + };
> +
> sysram@2020000 {
> compatible = "mmio-sram";
> reg = <0x02020000 0x54000>;
>
The exynos54xx.dtsi affects the exynos5410 SoC.
When I checked the PPI port number on Exynos5410/Exynos5422 TRM,
they have the different PPI port number as following:
|Exynos5410 |Exynos5422 |
----------------------------------------------------------------------------------------
ARCH_TIMER_PHYS_SECURE_PPI |1 nCNTPSIRQ |13 nCNTPSIRQ |Secure physical timer
ARCH_TIMER_PHYS_NONSECURE_PPI |2 nCNTPNSIRQ |14 nCNTPNSIRQ |Non-secure physical timer
ARCH_TIMER_VIRT_PPI |4 nCNTVIRQ |11 nCNTVIRQ |Virtual timer
ARCH_TIMER_HYP_PPI |5 nCNTHPIRQ |10 nCNTHPIRQ |Hypervisor timer
----------------------------------------------------------------------------------------
Exynos5410 and Exynos5422 have the different usage of bitfield
of nCNTPSIRQ/nCNTPNSIRQ/nCNTVIRQ/nCNTHPIRQ as following:
|Exynos5410 |Exynos5422
------------------------------------------------------------
nCNTPSIRQ[3:0] | KFC | EAGLE
nCNTPNSIRQ[3:0] | KFC | EAGLE
nCNTVIRQ[3:0] | KFC | EAGLE
nCNTHPIRQ[3:0] | KFC | EAGLE
------------------------------------------------------------
nCNTPSIRQ[7:4] | EAGLE | KFC
nCNTPNSIRQ[7:4] | EAGLE | KFC
nCNTVIRQ[7:4] | EAGLE | KFC
nCNTHPIRQ[7:4] | EAGLE | KFC
--
Best Regards,
Chanwoo Choi
Samsung Electronics
