Hi Sylwester,
On 2018-09-06 21:49, Sylwester Nawrocki wrote:
> On 08/29/2018 05:50 PM, Marek Szyprowski wrote:
>> Replace common suspend/resume handling code by generic helper.
>> Handling of PLLs is a bit different in generic code, as they are handled
>> in the same way as other clock registers. Such approach was already used
>> on later Exynos SoCs and worked fine. Tests have shown that it works also
>> on Exynos4 SoCs and significantly simplifies the code.
> I was going to ask whether it is safe to drop that PLL state polling code after
> looking at the diff but then I found it all explained in the commit message.
> Thank you for this clean up series, I have applied it to the samsung-clk tree.
> Thanks Chanwoo and Krzysztof for review and testing.
One more note which was lost in v2. I've tested this patch with system
suspend/resume on following Exynos4 boards: Trats (4210), Origen (4210),
OdroidU3 (4412) and Trats2 (4412). In all cases it worked fine.
>> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
>> ---
>> drivers/clk/samsung/clk-exynos4.c | 147 ++++--------------------------
>> 1 file changed, 16 insertions(+), 131 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
>> index 0421960eb963..d3bd9ffd8a09 100644
>> --- a/drivers/clk/samsung/clk-exynos4.c
>> +++ b/drivers/clk/samsung/clk-exynos4.c
>> @@ -16,7 +16,6 @@
>> -static void exynos4_clk_enable_pll(u32 reg)
>> -{
>> - u32 pll_con = readl(reg_base + reg);
>> - pll_con |= PLL_ENABLED;
>> - writel(pll_con, reg_base + reg);
>> -
>> - while (!(pll_con & PLL_LOCKED)) {
>> - cpu_relax();
>> - pll_con = readl(reg_base + reg);
>> - }
>> -}
>> -
>> -static void exynos4_clk_wait_for_pll(u32 reg)
>> -{
>> - u32 pll_con;
>> -
>> - pll_con = readl(reg_base + reg);
>> - if (!(pll_con & PLL_ENABLED))
>> - return;
>> -
>> - while (!(pll_con & PLL_LOCKED)) {
>> - cpu_relax();
>> - pll_con = readl(reg_base + reg);
>> - }
>> -}
>> -
>> -static int exynos4_clk_suspend(void)
>> -{
>> - exynos4_clk_enable_pll(EPLL_CON0);
>> - exynos4_clk_enable_pll(VPLL_CON0);
>> - return 0;
>> -}
> --
> Regards,
> Sylwester
>
>
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
