Hi Chanwoo,
On 2016-11-16 17:31, Chanwoo Choi wrote:
Hi Marek,
2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>:
This patch corrects FSYS CMU parent clocks specified in clock controller
node to let improved Exynos 5433 clocks driver to control proper clocks
on FSYS<->TOP CMU boundary.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 1188630..6564875 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -312,7 +312,7 @@
clock-names = "oscclk",
"sclk_ufs_mphy",
- "div_aclk_fsys_200",
+ "aclk_fsys_200",
FSYS cmu doesn't use the "aclk_fsys_200" clock as parent clock.
When I check the clk-exynos5433.c driver, CLK_MOUT_ACLK_FSYS_200_USER
mux in the FSYS cmu
uses the "div_aclk_fsys_200" clock as parent clock instead of "aclk_fsys_200".
Then this is a bug in clk-exynos5433.c driver. aclk_fsys_200 is the correct
parent for CLK_MOUT_ACLK_FSYS_200_USER mux. See page 582 and 814
(CLK_MUX_SEL_FSYS0 register description) of Exynos 5433 User Manual (rev
0.10).
Also my experiments revealed that aclk_fsys_200 gate register
(CLK_ACLK_FSYS_200 clk) has to be enabled to do any operation on devices in
FSYS block, so this is definitely the clock that is a parent of the whole
block.
I will prepare a fix for clk-exynos5433.c driver and dt bindings docs too.
"sclk_pcie_100_fsys",
"sclk_ufsunipro_fsys",
"sclk_mmc2_fsys",
@@ -322,7 +322,7 @@
"sclk_usbdrd30_fsys";
clocks = <&xxti>,
<&cmu_cpif CLK_SCLK_UFS_MPHY>,
- <&cmu_top CLK_DIV_ACLK_FSYS_200>,
+ <&cmu_top CLK_ACLK_FSYS_200>,
<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
<&cmu_top CLK_SCLK_MMC2_FSYS>,
--
1.9.1
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Best Regards,
Chanwoo Choi
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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