Hi Marek, 2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>: > This patch corrects FSYS CMU parent clocks specified in clock controller > node to let improved Exynos 5433 clocks driver to control proper clocks > on FSYS<->TOP CMU boundary. > > Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx> > --- > arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > index 1188630..6564875 100644 > --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > @@ -312,7 +312,7 @@ > > clock-names = "oscclk", > "sclk_ufs_mphy", > - "div_aclk_fsys_200", > + "aclk_fsys_200", FSYS cmu doesn't use the "aclk_fsys_200" clock as parent clock. When I check the clk-exynos5433.c driver, CLK_MOUT_ACLK_FSYS_200_USER mux in the FSYS cmu uses the "div_aclk_fsys_200" clock as parent clock instead of "aclk_fsys_200". > "sclk_pcie_100_fsys", > "sclk_ufsunipro_fsys", > "sclk_mmc2_fsys", > @@ -322,7 +322,7 @@ > "sclk_usbdrd30_fsys"; > clocks = <&xxti>, > <&cmu_cpif CLK_SCLK_UFS_MPHY>, > - <&cmu_top CLK_DIV_ACLK_FSYS_200>, > + <&cmu_top CLK_ACLK_FSYS_200>, > <&cmu_top CLK_SCLK_PCIE_100_FSYS>, > <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, > <&cmu_top CLK_SCLK_MMC2_FSYS>, > -- > 1.9.1 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in > the body of a message to majordomo@xxxxxxxxxxxxxxx > More majordomo info at http://vger.kernel.org/majordomo-info.html Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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