On 17-02-16, 15:55, Krzysztof Kozlowski wrote:
> On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and
> 12 steps for big core (700-1800 MHz). Add respective cooling cells.
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> index 261d25173f61..498ae82e1cb2 100644
> --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> @@ -33,6 +33,9 @@
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> + cooling-min-level = <0>;
> + cooling-max-level = <11>;
> + #cooling-cells = <2>; /* min followed by max */
> };
>
> cpu1: cpu@1 {
> @@ -70,6 +73,9 @@
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> + cooling-min-level = <0>;
> + cooling-max-level = <7>;
> + #cooling-cells = <2>; /* min followed by max */
> };
Though it wouldn't matter (for the issue you are getting), but this should be
added for all the CPUs in case some other CPU is booted first.
--
viresh
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