Add support for restoring GScaler parent clocks configuration when GSCL
power domain is turned on.
Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
---
arch/arm/boot/dts/exynos5420.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 48a0a55..912143e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -252,8 +252,10 @@
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
#power-domain-cells = <0>;
- clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
- clock-names = "asb0", "asb1";
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK300_GSCL>,
+ <&clock CLK_MOUT_USER_ACLK300_GSCL>, <&clock CLK_GSCL0>,
+ <&clock CLK_GSCL1>;
+ clock-names = "oscclk", "pclk0", "clk0", "asb0", "asb1";
};
isp_pd: power-domain@10044020 {
--
1.9.2
--
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