On 26.08.2015 12:30, Alim Akhtar wrote: > As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV > and the GATE clocks are at bit 16 in their respective registers. > For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1. > And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1. > This patch corrects it. > This also adds xxx_FSYS11 to be saved/restore during s2r cycles. > > Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx> > --- > drivers/clk/samsung/clk-exynos7.c | 24 +++++++++++++++--------- > 1 file changed, 15 insertions(+), 9 deletions(-) > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@xxxxxxxxxxx> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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