On 26.08.2015 12:30, Alim Akhtar wrote: > Corrects the bit width of DIV_TOPC3 register. > These are worngly set to 3 which should be 4 bit wide as per UM. > This also adjusts the MUX clock order. > > Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx> > --- > drivers/clk/samsung/clk-exynos7.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@xxxxxxxxxxx> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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