Hi Sylwester,
On 01/29/2015 09:53 PM, Sylwester Nawrocki wrote:
> Hi Chanwoo,
>
> On 23/01/15 21:54, Chanwoo Choi wrote:
>> On Sat, Jan 24, 2015 at 2:40 AM, Sylwester Nawrocki
>> <s.nawrocki@xxxxxxxxxxx> wrote:
>>> On 21/01/15 07:26, Chanwoo Choi wrote:
>>>> +/* list of all parent clock list */
>>>
>>>> +PNAME(mout_bus_pll_user_p) = { "fin_pll", "sclk_bus_pll", };
>>> ...
>>>> +
>>>> +static struct samsung_mux_clock top_mux_clks[] __initdata = {
>>>
>>>> + MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
>>>> + MUX_SEL_TOP1, 0, 1),
>>> ...
>>>> +};
>>>> +
>>>> +static struct samsung_div_clock top_div_clks[] __initdata = {
>>> ...
>>>> + /* DIV_TOP3 */
>>>> + DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
>>>> + "mout_bus_pll_user", DIV_TOP3, 24, 3),
>>>
>>> Shouldn't "fin_pll" be renamed to "oscclk" ? In the documentation
>>> the root clock (from XXTI input pin) seems to be referred as OSCCLK.
>>> And I can't see "fin_pll" clock registered anywhere. Shouldn't there
>>> be a "fixed-rate-clock" as a parent of at least CMU_TOP? e.g.
>>
>> Right,
>> I added "fin_pll" fixed clock in DT as following:
>> When I registered "fin_pll" fixed clock, I could use "fin_pll" clock
>> for exynos5433 cmu without adding additional dt node.
>>
>> fin_pll: xxti {
>> compatible = "fixed-clock";
>> clock-output-names = "fin_pll";
>> #clock-cells = <0>;
>> };
>>
>> I'll add the example of "fin_pll" dt node to documentation for exynos5433 cmu.
>
> OK, thanks. But I think it needs to be named "oscclk", FIN_PLL is almost
> not existent in the SoC's documentation.
> I'd suggest to define the root oscillator clock (XXTI/OSCCLK) as "oscclk"
> in DT, rather than registering "fin_pll" fixed clock in the driver.
OK,
I'll fix it by using "oscclk" clock name instead of "fin_pll".
>
>>> xxti: xxti {
>>> compatible = "fixed-clock";
>>> #clock-cells = <0>;
>>> clock-output-names = "oscclk";
>>> clock-frequency = <24000000>;
>>> };
>>>
>>> &cmu_top {
>>> clocks = <&xxti>;
>>> };
Best Regards,
Chanwoo Choi
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