>
> This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
> following memory buses to translate data between DRAM and eMMC/sub-IPs.
>
> Following list specifies the detailed relation between memory bus clock and DMC
> IP in MIF (Memory Interface) block:
> - DMC clock : DMC (Dynamic Memory Controller)
>
> Following list specifies the detailed relation between memory bus clock and
> sub-IPs in INT (Internal) block:
> - ACLK100 clock : PERIL
> - ACLK160 clock : LCD0
> - ACLK200 clock : FSYS
> - ACLK266 clock : ISP
> - GDL/GDR clock : leftbus/rightbus
> - SCLK_MFC clock : MFC
>
> Cc: Kukjin Kim <kgene@xxxxxxxxxx>
> Cc: Myungjoo Ham <myungjoo.ham@xxxxxxxxxxx>
> Cc: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
> Signed-off-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
> Acked-by: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
Acked-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx>
> ---
> arch/arm/boot/dts/exynos3250.dtsi | 125 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 125 insertions(+)
>
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