Hi ~
On Wed, Jul 30, 2014 at 5:07 PM, Thomas Abraham <thomas.ab@xxxxxxxxxxx> wrote:
> +
> +/* handler for post-rate change notification from parent clock */
> +static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
> + struct exynos_cpuclk *cpuclk, void __iomem *base)
> +{
> + const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
> + unsigned long div = 0, div_mask = DIV_MASK;
> + unsigned long mux_reg;
> +
> + spin_lock(cpuclk->lock);
> +
> + /* select mout_apll as the alternate parent */
> + mux_reg = readl(base + E4210_SRC_CPU);
> + writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
> + wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
> +
> + if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
> + /* find out the divider values to use for clock data */
> + while ((cfg_data->prate * 1000) != ndata->new_rate) {
> + if (cfg_data->prate == 0)
missing spin_unlock(cpuclk->lock);?
I think that spin_unlock should be added in here..
> + return -EINVAL;
> + cfg_data++;
> + }
> +
> + div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
> + div_mask |= E4210_DIV0_ATB_MASK;
> + }
> +
> + exynos_set_safe_div(base, div, div_mask);
> + spin_unlock(cpuclk->lock);
> + return 0;
> +}
> +
>
Best regards,
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