Hi Kukjin,
On Wed, May 21, 2014 at 5:47 AM, Kukjin Kim <kgene.kim@xxxxxxxxxxx> wrote:
> Yeah, actually we don't need to reset the count value after suspend/resume.
> So, how about following? I think, it should be fine to you.
>
> diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
> index 8d64200..d24db6f 100644
> --- a/drivers/clocksource/exynos_mct.c
> +++ b/drivers/clocksource/exynos_mct.c
> @@ -157,12 +157,15 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
> {
> u32 reg;
>
> - exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
> - exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
> -
> reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
> - reg |= MCT_G_TCON_START;
> - exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
> +
> + if (!(reg & MCT_G_TCON_START)) {
> + exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
> + exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
> +
> + reg |= MCT_G_TCON_START;
> + exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
> + }
> }
>
>
As Doug mentioned, this seems more complicated than necessary since
the kernel doesn't care about the initial value of the mct counter at
all. Is there some reason from a hardware standpoint that the counter
needs to be cleared? If not, I would rather just delete the two
offending lines. I am sending a patch that does this instead.
Cheers,
Chirantan
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