Re: clk: Exynos5250: Add clocks for G3D

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Arun,

On Tue, May 21, 2013 at 5:36 AM, Arun Kumar K <arun.kk@xxxxxxxxxxx> wrote:
> @@ -262,6 +270,7 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
>         DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
>         DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
>         DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
> +       DIV(aclk_400_g3d, "aclk_400_g3d", "mout_aclk400", DIV_TOP0, 24, 3),

Doh!  I looked at this more and it looks like I missed something.
You've added this clock to the range assigned for "[Peripheral Clock
Gates]".  This is not a gate clock but is a div clock.

Perhaps it should be in a different range?  Could make IDs that start
at 512 or something?

-Doug
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