RE: [PATCH 1/2] ARM: EXYNOS: Update HSOTG PHY clock setting for Exynos4x12

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Sachin Kamat wrote:
> 
> Adds clock setting entries for Exynos4212 and Exynos4412 platforms.
> 
> Signed-off-by: Sachin Kamat <sachin.kamat@xxxxxxxxxx>
> ---
> Based on Kukjin Kim's v3.5-for-usb-2 branch.
> ---
>  arch/arm/mach-exynos/include/mach/regs-usb-phy.h |    5 ++
>  arch/arm/mach-exynos/setup-usb-phy.c             |   47
++++++++++++++++-----
>  arch/arm/plat-samsung/include/plat/cpu.h         |    4 ++
>  3 files changed, 45 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> index c337cf3..bab28d9 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
> @@ -38,8 +38,13 @@
>  #define CLKSEL_MASK			(0x3 << 0)
>  #define CLKSEL_SHIFT			(0)
>  #define CLKSEL_48M			(0x0 << 0)
> +#define CLKSEL_9600K			(0x0 << 0)
> +#define CLKSEL_10M			(0x1 << 0)
>  #define CLKSEL_12M			(0x2 << 0)
> +#define CLKSEL_19200K			(0x3 << 0)
>  #define CLKSEL_24M			(0x3 << 0)
> +#define CLKSEL_20M			(0x4 << 0)
> +#define EXYNOS4X12_CLKSEL_24M		(0x5 << 0)
> 

I would preferred following to avoid confusion. Of course, need to update
regarding file accordingly.

@@ -35,11 +35,21 @@
 #define PHY1_COMMON_ON_N		(1 << 7)
 #define PHY0_COMMON_ON_N		(1 << 4)
 #define PHY0_ID_PULLUP			(1 << 2)
-#define CLKSEL_MASK			(0x3 << 0)
-#define CLKSEL_SHIFT			(0)
-#define CLKSEL_48M			(0x0 << 0)
-#define CLKSEL_12M			(0x2 << 0)
-#define CLKSEL_24M			(0x3 << 0)
+
+#define EXYNOS4_CLKSEL_SHIFT		(0)
+
+#define EXYNOS4210_CLKSEL_MASK		(0x3 << 0)
+#define EXYNOS4210_CLKSEL_48M		(0x0 << 0)
+#define EXYNOS4210_CLKSEL_12M		(0x2 << 0)
+#define EXYNOS4210_CLKSEL_24M		(0x3 << 0)
+
+#define EXYNOS4X12_CLKSEL_MASK		(0x7 << 0)
+#define EXYNOS4X12_CLKSEL_9600K		(0x0 << 0)
+#define EXYNOS4X12_CLKSEL_10M		(0x1 << 0)
+#define EXYNOS4X12_CLKSEL_12M		(0x2 << 0)
+#define EXYNOS4X12_CLKSEL_19200K	(0x3 << 0)
+#define EXYNOS4X12_CLKSEL_20M		(0x4 << 0)
+#define EXYNOS4X12_CLKSEL_24M		(0x5 << 0)
 
 #define EXYNOS4_RSTCON			EXYNOS4_HSOTG_PHYREG(0x08)
 #define HOST_LINK_PORT_SWRST_MASK	(0xf << 6)

[...]

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@xxxxxxxxxxx>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

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