[PATCH 1/2] ARM: EXYNOS: Update HSOTG PHY clock setting for Exynos4x12

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Adds clock setting entries for Exynos4212 and Exynos4412 platforms.

Signed-off-by: Sachin Kamat <sachin.kamat@xxxxxxxxxx>
---
Based on Kukjin Kim's v3.5-for-usb-2 branch.
---
 arch/arm/mach-exynos/include/mach/regs-usb-phy.h |    5 ++
 arch/arm/mach-exynos/setup-usb-phy.c             |   47 ++++++++++++++++-----
 arch/arm/plat-samsung/include/plat/cpu.h         |    4 ++
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
index c337cf3..bab28d9 100644
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -38,8 +38,13 @@
 #define CLKSEL_MASK			(0x3 << 0)
 #define CLKSEL_SHIFT			(0)
 #define CLKSEL_48M			(0x0 << 0)
+#define CLKSEL_9600K			(0x0 << 0)
+#define CLKSEL_10M			(0x1 << 0)
 #define CLKSEL_12M			(0x2 << 0)
+#define CLKSEL_19200K			(0x3 << 0)
 #define CLKSEL_24M			(0x3 << 0)
+#define CLKSEL_20M			(0x4 << 0)
+#define EXYNOS4X12_CLKSEL_24M		(0x5 << 0)
 
 #define EXYNOS4_RSTCON			EXYNOS4_HSOTG_PHYREG(0x08)
 #define HOST_LINK_PORT_SWRST_MASK	(0xf << 6)
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 1af0a7f..b8cf0f8 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -36,17 +36,42 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
 
 	xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
 	if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-		switch (clk_get_rate(xusbxti_clk)) {
-		case 12 * MHZ:
-			phyclk |= CLKSEL_12M;
-			break;
-		case 24 * MHZ:
-			phyclk |= CLKSEL_24M;
-			break;
-		default:
-		case 48 * MHZ:
-			/* default reference clock */
-			break;
+		if (soc_is_exynos4210()) {
+			switch (clk_get_rate(xusbxti_clk)) {
+			case 12 * MHZ:
+				phyclk |= CLKSEL_12M;
+				break;
+			case 24 * MHZ:
+				phyclk |= CLKSEL_24M;
+				break;
+			default:
+			case 48 * MHZ:
+				/* default reference clock */
+				break;
+			}
+		} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+			switch (clk_get_rate(xusbxti_clk)) {
+			case 9600 * KHZ:
+				phyclk |= CLKSEL_9600K;
+				break;
+			case 10 * MHZ:
+				phyclk |= CLKSEL_10M;
+				break;
+			case 12 * MHZ:
+				phyclk |= CLKSEL_12M;
+				break;
+			case 19200 * KHZ:
+				phyclk |= CLKSEL_19200K;
+				break;
+			case 20 * MHZ:
+				phyclk |= CLKSEL_20M;
+				break;
+			default:
+			case 24 * MHZ:
+				/* default reference clock */
+				phyclk |= EXYNOS4X12_CLKSEL_24M;
+				break;
+			}
 		}
 		clk_put(xusbxti_clk);
 	}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 787ceac..6a6ff7e 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
+#ifndef KHZ
+#define KHZ (1000)
+#endif
+
 #ifndef MHZ
 #define MHZ (1000*1000)
 #endif
-- 
1.7.4.1

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