Tushar Behera wrote:
>
> Amba core assumes the pclk to be named as apb_pclk. During device probe,
> it tries to get that clock and enable that. When PM_RUNTIME is enabled,
> dma clock is not explicitly enabled in pl330_probe, which causes device
> probe to fail. Adding a clkdev entry for apb_pclk for mdma1 fixes the
> problem.
>
> This patch fixes following runtime error.
>
> dma-pl330 dma-pl330.2: PERIPH_ID 0x0, PCELL_ID 0x0 !
> dma-pl330: probe of dma-pl330.2 failed with error -22
>
> Signed-off-by: Tushar Behera <tushar.behera@xxxxxxxxxx>
> ---
> arch/arm/mach-exynos/clock.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
> index 28e2842..eb33a7a 100644
> --- a/arch/arm/mach-exynos/clock.c
> +++ b/arch/arm/mach-exynos/clock.c
> @@ -1326,6 +1326,7 @@ static struct clk_lookup exynos4_clk_lookup[] = {
> CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
> CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
> CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
> + CLKDEV_INIT("dma-pl330.2", "apb_pclk", &clk_mdma1),
> };
>
> static int xtal_rate;
> --
> 1.7.4.1
Looks ok to me, will apply.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@xxxxxxxxxxx>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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