From: Thomas Abraham <thomas.ab@xxxxxxxxxxx>
This patch sets up the module clock for all instances of SDHCI
controller. The source clock for the controller is set as
dout_mpll and the controller clock rate is set to 50MHz.
Signed-off-by: Thomas Abraham <thomas.ab@xxxxxxxxxxx>
---
arch/arm/plat-s3c64xx/s3c6400-clock.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 8c5057c..349159a 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -711,8 +711,16 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
clk_p.rate = pclk;
clk_f.rate = fclk;
+ clk_set_parent(&clk_mmc0.clk, &clk_dout_mpll);
+ clk_set_parent(&clk_mmc1.clk, &clk_dout_mpll);
+ clk_set_parent(&clk_mmc2.clk, &clk_dout_mpll);
+
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c6400_set_clksrc(init_parents[ptr]);
+
+ clk_set_rate(&clk_mmc0.clk, 50*MHZ);
+ clk_set_rate(&clk_mmc1.clk, 50*MHZ);
+ clk_set_rate(&clk_mmc2.clk, 50*MHZ);
}
static struct clk *clks[] __initdata = {
--
1.5.3.4
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