On 10/5/21 1:56 PM, Janosch Frank wrote:
> On 10/5/21 11:09, Janis Schoetterl-Glausch wrote:
>> Generate specification exceptions and check that they occur.
>> With the iterations argument one can check if specification
>> exception interpretation occurs, e.g. by using a high value and
>> checking that the debugfs counters are substantially lower.
>> The argument is also useful for estimating the performance benefit
>> of interpretation.
>>
>> Signed-off-by: Janis Schoetterl-Glausch <scgl@xxxxxxxxxxxxx>
>> ---
>> s390x/Makefile | 1 +
>> s390x/spec_ex.c | 182 ++++++++++++++++++++++++++++++++++++++++++++
>> s390x/unittests.cfg | 3 +
>> 3 files changed, 186 insertions(+)
>> create mode 100644 s390x/spec_ex.c
>>
>> diff --git a/s390x/Makefile b/s390x/Makefile
>> index ef8041a..57d7c9e 100644
>> --- a/s390x/Makefile
>> +++ b/s390x/Makefile
>> @@ -24,6 +24,7 @@ tests += $(TEST_DIR)/mvpg.elf
>> tests += $(TEST_DIR)/uv-host.elf
>> tests += $(TEST_DIR)/edat.elf
>> tests += $(TEST_DIR)/mvpg-sie.elf
>> +tests += $(TEST_DIR)/spec_ex.elf
>> tests_binary = $(patsubst %.elf,%.bin,$(tests))
>> ifneq ($(HOST_KEY_DOCUMENT),)
>> diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
>> new file mode 100644
>> index 0000000..dd0ee53
>> --- /dev/null
>> +++ b/s390x/spec_ex.c
>> @@ -0,0 +1,182 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * © Copyright IBM Corp. 2021
>> + *
>> + * Specification exception test.
>> + * Tests that specification exceptions occur when expected.
>> + */
>> +#include <stdlib.h>
>> +#include <libcflat.h>
>> +#include <asm/interrupt.h>
>> +#include <asm/facility.h>
>> +
>> +static struct lowcore *lc = (struct lowcore *) 0;
>> +
>> +static bool expect_invalid_psw;
>> +static struct psw expected_psw;
>> +static struct psw fixup_psw;
>> +
>> +/* The standard program exception handler cannot deal with invalid old PSWs,
>> + * especially not invalid instruction addresses, as in that case one cannot
>> + * find the instruction following the faulting one from the old PSW.
>> + * The PSW to return to is set by load_psw.
>> + */
>> +static void fixup_invalid_psw(void)
>> +{
>> + if (expect_invalid_psw) {
>> + report(expected_psw.mask == lc->pgm_old_psw.mask
>> + && expected_psw.addr == lc->pgm_old_psw.addr,
>> + "Invalid program new PSW as expected");
>> + expect_invalid_psw = false;
>> + }
>> + lc->pgm_old_psw = fixup_psw;
>> +}
>> +
>> +static void load_psw(struct psw psw)
>> +{
>> + uint64_t r0 = 0, r1 = 0;
>> +
>> + asm volatile (
>> + " epsw %0,%1\n"
>> + " st %0,%[mask]\n"
>> + " st %1,4+%[mask]\n"
>
> You're grabbing the mask for the fixup psw, right?
Yes
> Why don't you use the extract_psw_mask() function for that?
No reason, sounds like a good idea to use the function.
>
> Also I'd recommend not mixing named operands and numeric operands, especially when the variables are then called r0 and r1.
I suppose I didn't name them because they're just scratch registers.
But using extract_psw_mask() will get rid of them anyway
>
>> + " larl %0,nop%=\n"
>> + " stg %0,%[addr]\n"
>
> This stores the address of the nop to the fixup psw addr.
> So far so good, but why is it only called "addr"?
>
>> + " lpswe %[psw]\n"
>> + "nop%=: nop\n"
>> + : "+&r"(r0), "+&a"(r1), [mask] "=&R"(fixup_psw.mask),
>> + [addr] "=&R"(fixup_psw.addr)
>> + : [psw] "Q"(psw)
>> + : "cc", "memory"
>> + );
>
> You made this a bit complicated and didn't document it.
> /*
> * Setup fixup_psw before loading an invalid PSW so that *fixup_invalid_psw() can bring us back onto the right track.
> */
> >> +}
>> +
>> +static void psw_bit_12_is_1(void)
>> +{
>> + expected_psw.mask = 0x0008000000000000;
>> + expected_psw.addr = 0x00000000deadbeee;
>> + expect_invalid_psw = true;
>> + load_psw(expected_psw);
>> +}
>> +
[...]
