On 10/04/2020 19:26:58+0300, Claudiu Beznea wrote:
> Add RTT.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx>
> ---
> arch/arm/boot/dts/at91-sam9x60ek.dts | 5 +++++
> arch/arm/boot/dts/sam9x60.dtsi | 7 +++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
> index ab3d2d9a420a..4020e79a958e 100644
> --- a/arch/arm/boot/dts/at91-sam9x60ek.dts
> +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
> @@ -617,6 +617,11 @@
> };
> };
>
> +&rtt {
> + atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
> + status = "okay";
Is there any point using a gpbr register while there is already a much
better RTC in the system?
In any case, this diff should be merge with the other at91-sam9x60ek.dts
change instead of being with the dtsi change.
> +};
> +
> &shutdown_controller {
> atmel,shdwc-debouncer = <976>;
> status = "okay";
> diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
> index 326b39328b58..e1d8e3a4cb0b 100644
> --- a/arch/arm/boot/dts/sam9x60.dtsi
> +++ b/arch/arm/boot/dts/sam9x60.dtsi
> @@ -661,6 +661,13 @@
> status = "disabled";
> };
>
> + rtt: rtt@fffffe20 {
> + compatible = "microchip,sam9x60-rtt";
> + reg = <0xfffffe20 0x20>;
> + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&clk32k 0>;
> + };
> +
> pit: timer@fffffe40 {
> compatible = "atmel,at91sam9260-pit";
> reg = <0xfffffe40 0x10>;
> --
> 2.7.4
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
