On Wed, Apr 26 2023 at 12:03, Zdenek Bouska wrote:
> following patch is my current approach for fixing this issue. I introduced
> big_cpu_relax(), which uses Will's implementation [1] on ARM64 without
> LSE atomics and original cpu_relax() on any other CPU.
Why is this interrupt handling specific? Just because it's the place
where you observed it?
That's a general issue for any code which uses atomics for forward
progress. LL/SC simply does not guarantee that.
So if that helps, then this needs to be addressed globaly and not with
some crude hack in the interrupt handling code.
> Anyone has a better idea how to solve this issue properly?
Use hardware with LSE atomics :)
Thanks,
tglx
