Invalidating and flushing all caches may introduce long latencies of up
to several milliseconds. Do not execute it in PREEMPT_RT_FULL kernels,
warn once instead and propose to pin all GPU renderering tasks to a
single CPU, if possible.
Original commit:
25ff1195f8a0b3724541ae7bbe331b4296de9c06 upstream.
Original log:
In order to fully serialize access to the fenced region and the update
to the fence register we need to take extreme measures on SNB+, and
manually flush writes to memory prior to writing the fence register in
conjunction with the memory barriers placed around the register write.
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Signed-off-by: Carsten Emde <C.Emde@xxxxxxxxx>
---
i915_gem.c | 26 ++++----------------------
1 file changed, 4 insertions(+), 22 deletions(-)
Index: linux-3.8.13-rt10/drivers/gpu/drm/i915/i915_gem.c
===================================================================
--- linux-3.8.13-rt10.orig/drivers/gpu/drm/i915/i915_gem.c
+++ linux-3.8.13-rt10/drivers/gpu/drm/i915/i915_gem.c
@@ -2656,10 +2656,12 @@ static inline int fence_number(struct dr
return fence - dev_priv->fence_regs;
}
+#ifndef CONFIG_PREEMPT_RT_FULL
static void i915_gem_write_fence__ipi(void *data)
{
wbinvd();
}
+#endif
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
struct drm_i915_fence_reg *fence,
@@ -2679,8 +2681,18 @@ static void i915_gem_object_update_fence
* on each processor in order to manually flush all memory
* transactions before updating the fence register.
*/
+#ifdef CONFIG_PREEMPT_RT_FULL
+ if (HAS_LLC(obj->base.dev)) {
+ WARN_ONCE(1, "Cannot flush caches on RT"
+#ifdef CONFIG_SMP
+ ", please pin rendering tasks to a single CPU"
+#endif
+ "\n");
+ }
+#else
if (HAS_LLC(obj->base.dev))
on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
+#endif
i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
if (enable) {
--
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