On 2019-12-30 12:09 am, Jonas Karlman wrote:
On 2019-12-29 21:14, Robin Murphy wrote:
Add OPPs for the GPU, derived from the downstream Beelink A1 DTB.
My RK3328 devices (rock64, roc-cc and other android tv boxes) used to become
unstable when I used similar OPPs as these and vdd_logic got changed to anything
below 1.05v some time ago, network speeds slowed down and devices usually
become unresponsive.
I do use vendor ddr init blobs to run ddr at 786 or 933 MHz, gpu runs at 500 Mhz
and rock64/roc-cc LDO3 is set to use 1.0v instead of 1.1v used in A1 dts,
in case that could be affecting the stability at lower vdd_logic voltages.
These observations was a few months back so I will redo some tests and see if I
still get unstable systems using anything below default 1.1v for vdd_logic.
Indeed, as noted on the lima devfreq thread it turns out voltage scaling
wasn't actually happening, so things weren't as thoroughly exercised as
I might have thought. I do note that downstream appears to have DRAM
DVFS also operating on the VDD_LOGIC domain (not to mention the video
decoder), so it's quite possible that in lieu of that we might need to
forcibly limit the minimum voltage as a compromise.
Thanks,
Robin.
Best regards,
Jonas
Signed-off-by: Robin Murphy <robin.murphy@xxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 91306ebed4da..e1b1b4551a8b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -605,6 +605,28 @@
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
resets = <&cru SRST_GPU_A>;
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpu_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1125000>;
+ };
};
h265e_mmu: iommu@ff330200 {
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