Am Montag, 26. Februar 2018, 19:57:21 CET schrieb Vicente Bergas:
> The PCIe signals are routed through the connector to the baseboard.
>
> Signed-off-by: Vicente Bergas <vicencb at gmail.com>
> Tested-by: Vicente Bergas <vicencb at gmail.com>
> ---
> .../arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 15
> +++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi |
> 15 --------------- 2 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
> b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index
> 56952d1a3fb8..4d47150d6862 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
> @@ -190,6 +190,21 @@
> status = "okay";
> };
>
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
> + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
> + assigned-clock-rates = <100000000>;
> + ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
I've applied both patches into a temporary branch for likely 4.18 now
with the tags from Shawn.
Reason is that we also have a fix for 4.16 in a different branch fixing
the ep-gpios property on sapphire and having these things conflict
will end up in a lot of chaos, as that fix is not yet in the mainline kernel
but only in an intermediate state.
So likely the pcie move will have to wait for 4.18 to make it easier
on everybody.
Heiko
