Kishon, Am Donnerstag, 19. November 2015, 22:22:28 schrieb Heiko Stuebner: > The otgphy clocks really only drive the phy blocks. These in turn > contain plls that then generate the 480m clocks the clock controller > uses to supply some other clocks like uart0, gpu or the video-codec. > > So fix this structure to actually respect that hirarchy and removed > that usb480m fixed-rate clock working as a placeholder till now, as > this wouldn't even work if the supplying phy gets turned off while > its pll-output gets used elsewhere. > > Signed-off-by: Heiko Stuebner <heiko at sntech.de> > Reviewed-by: Douglas Anderson <dianders at chromium.org> it looks like this patch didn't make your cutoff time for sending your stuff to Greg. As the core phy series up to patch 5 is in mainline now, I've just applied this patch to my clk-branch for 4.6. Heiko