Hi, On Mon, Oct 20, 2014 at 4:27 PM, Doug Anderson <dianders at chromium.org> wrote: > @@ -1464,15 +1474,20 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) > if (ret < 0) > return ret; > > + spin_lock_irqsave(&bank->slock, flags); > + > data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); > data &= ~mask; > writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); > > + spin_unlock_irqrestore(&bank->slock, flags); > + > if (type & IRQ_TYPE_EDGE_BOTH) > __irq_set_handler_locked(d->irq, handle_edge_irq); > else > __irq_set_handler_locked(d->irq, handle_level_irq); > > + spin_lock_irqsave(&bank->slock, flags); > irq_gc_lock(gc); > > level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); > @@ -1522,6 +1537,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) > writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); > > irq_gc_unlock(gc); > + spin_unlock_irqrestore(&bank->slock, flags); I just reviewed this again myself and I realized that there was an error path case that I missed. I'll plan to spin tomorrow and include any extra feedback people have. I'll also note that I'd love any extra scrutiny people have on this patch. I'm submitting it totally based on code inspection and am nowhere near an expert on this driver. I mostly just looked for all of the read/modify/wites using writel and added the lock... -Doug
