Hi, > Yeah, it just highlights we that we need some way to test this. Apart from > my buggy code we also don't really know how the hw reacts to writing the > divider in the middle of a transfer... I finally got around to stress-testing this patch with rate changes forced from a test driver [1]. Here are waveforms for rate transitions: Rate change from default rate to half rate: http://x-quadraht.de/fast_to_slow.png >From half rate to default rate: http://x-quadraht.de/slow_to_fast.png The third and fourth line show the begin and end of the clk_set_rate() call, respectively. You can see nicely that both rate transitions result in a few slower SCL cycles, but never in faster ones. As soon as Addy's divider calculation patch is accepted, I will rebase the patch and send it again. Cheers, Max [1]: https://gist.github.com/xqms/086bec7269df64f46b14 Note: The driver requires exporting the __clk_lookup function from clk.c.
