Hi Geert, Thank you for the review. On Fri, Mar 14, 2025 at 1:04 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Sun, 9 Mar 2025 at 22:14, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Refactor PLL handling by introducing a `struct pll` to encapsulate PLL > > configuration parameters, ensuring consistency with the existing dynamic > > divider structure. > > > > Introduce the `PLL_PACK()` macro to simplify PLL structure initialization > > and update the `DEF_PLL()` macro to use the new `pll` structure. Modify > > relevant clock register functions to utilize the structured PLL data > > instead of raw configuration values. > > > > This refactoring improves code readability, maintainability, and > > alignment with the existing clock configuration approach. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > i.e. will queue in renesas-clk for v6.16. > > > --- a/drivers/clk/renesas/rzv2h-cpg.h > > +++ b/drivers/clk/renesas/rzv2h-cpg.h > > @@ -10,6 +10,25 @@ > > > > #include <linux/bitfield.h> > > > > +/** > > + * struct pll - Structure for PLL configuration > > + * > > + * @offset: STBY register offset > > + * @clk: Flag to indicate if CLK1/2 are accessible or not > > If you don't mind, I'll rename this to "has_clkn" while applying. > sounds good to me, thank you for taking care of it. Cheers, Prabhakar
