From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Hi All, This patch series introduces support for enabling PLL clocks in the RZ/V2H(P) CPG family driver and adds clock and reset entries for the GE3D module. v1->v2 - Simplified PLL conf handling as suggested by Geert - Updated macros to get PLL configuration offsets - Minor cleanups Cheers, Prabhakar Lad Prabhakar (5): clk: renesas: rzv2h: Refactor PLL configuration handling clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk` clk: renesas: rzv2h-cpg: Add support for enabling PLLs clk: renesas: rzv2h: Rename PLL field macros for consistency clk: renesas: r9a09g057: Add clock and reset entries for GE3D drivers/clk/renesas/r9a09g047-cpg.c | 2 +- drivers/clk/renesas/r9a09g057-cpg.c | 16 +++++- drivers/clk/renesas/rzv2h-cpg.c | 78 +++++++++++++++++++++++------ drivers/clk/renesas/rzv2h-cpg.h | 32 +++++++++--- 4 files changed, 104 insertions(+), 24 deletions(-) -- 2.43.0
