From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Move the `PLL_CLK_ACCESS()`, `PLL_CLK1_OFFSET()`, and `PLL_CLK2_OFFSET()`
macros from `rzv2h-cpg.h` to `rzv2h-cpg.c`, as they are not intended for
use by SoC-specific CPG drivers.
Additionally, update `PLL_CLK1_OFFSET()` and `PLL_CLK2_OFFSET()` to use
the `FIELD_GET()` macro for better readability and simplify the
`PLL_CLK_ACCESS()` macro.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
drivers/clk/renesas/rzv2h-cpg.c | 4 ++++
drivers/clk/renesas/rzv2h-cpg.h | 3 ---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 419dc8cd2766..1ebaefb36133 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -56,6 +56,10 @@
#define CPG_CLKSTATUS0 (0x700)
+#define PLL_CLK_ACCESS(n) (!!((n) & BIT(31)))
+#define PLL_CLK1_OFFSET(n) FIELD_GET(GENMASK(15, 0), (n))
+#define PLL_CLK2_OFFSET(n) (PLL_CLK1_OFFSET(n) + (0x4))
+
/**
* struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
*
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index fd8eb985c75b..81f44b94f6d5 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -87,9 +87,6 @@ enum clk_types {
/* BIT(31) indicates if CLK1/2 are accessible or not */
#define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16)))
-#define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0)
-#define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16))
-#define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4))
#define DEF_TYPE(_name, _id, _type...) \
{ .name = _name, .id = _id, .type = _type }
--
2.43.0
